A new smart memory controller with DMA support has been developed
- Details
- Published: Friday, 10 October 2014 21:08
 |
Memory controller overall scheme |
A new version of the smart memory controller has been developed and tested. Now the controller maintains block data transfers - usually this calls ‘DMA’ - a system, enabling to copy data from one memory area to another without involving processing cores. The usage of the mechanism allows to increase performance of intensive data exchange tasks in several times. There is a basic set of "real" atomic operations in the controller, for instance, atomic increment is supported.
The new memory controller, as well as its previous version, maintains FE bit mechanism. The mechanism allows to implement memory access synchronization from various threads. In particular, the controller enables to interrupt thread execution in case the requested data has not been received yet and to resume the thread almost instantly right after the data is ready.
All of the above mechanisms are implemented on the hardware layer which provides maximum performance and energy efficiency.
